Semiconductor device with alternating conductivity type layer and method of manufacturing the same
Patent 6291856 Issued on September 18, 2001. Estimated Expiration Date: 
November 10, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 10, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor power devices with alternating conductivity type high-voltage breakdown regions Power MOSFET High voltage mosfet structure Semiconductor device having a plurality of parallel drift regions Field effect-controlled semiconductor component Patent #: 6184555 InventorsAssigneeApplicationNo. 438078 filed on 11/10/1999US Classes:257/335, Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)257/341, Plural sections connected in parallel (e.g., power MOSFET)257/342, With means to reduce ON resistance257/E29.066, Body region structure of IGFET's with channel containing layer (DMOSFET or IGBT) (EPO)257/E29.198, Transistor with vertical current flow (EPO)257/E29.257Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)ExaminersPrimary: Ngo, Hung V.Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/76H01L 029/94 H01L 031/062 H01L 031/113 H01L 031/119 Foreign Application Priority Data1998-11-12 JPAbstractThis invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.Other References
Field of SearchActive channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)With lightly doped portion of drain region adjacent channel (e.g., LDD structure) In integrated circuit structure Plural sections connected in parallel (e.g., power MOSFET) With means to reduce ON resistance | |
