Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
March 15, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital phase lock clock generator without local oscillator Apparatus and method for selecting a tap range in a digital delay line Synchronous clock generator including delay-locked loop Synchronous clock generator including a delay-locked loop signal loss detector Circuitry for the delay adjustment of a clock signal Method and apparatus for improving the performance of digital delay locked loop circuits Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution Patent #: 6137325 InventorAssigneeApplicationNo. 525780 filed on 03/15/2000US Classes:327/156, Phase lock loop327/160, With counter327/161With delay meansExaminersPrimary: Callahan, Timothy P.Assistant: Nguyen, Hiep T. Attorney, Agent or FirmInternational ClassesH03L 007/06255 256 257 155 AbstractAn inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor. A second multiplexer then selects and outputs the second output clock from among the second series of delayed clocks in accordance with the second count. As a result, at least one of the clocks is generated with improved resolution over conventional DLLs.Field of SearchWith variable delay meansSynchronizing With feedback Phase lock loop With variable delay means With counter With choice between multiple delayed clocks With delay means With feedforward Phase lock loop With counter With delay means By phase Phase shift by less than period of input Quadrature related (i.e., 90 degrees) With phase comparator or detector Having multiple outputs Quadrature related (i.e., 90 degrees) | |
