U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

High speed video frame buffer

Patent 6278645 Issued on August 21, 2001. Estimated Expiration Date: Icon_subject August 5, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Graphics system with shadow ram update to the color map
Patent #: 5170468
Issued on: 12/08/1992
Inventor: Shah, et al.

Synchronization techniques for multimedia data streams
Patent #: 5333299
Issued on: 07/26/1994
Inventor: Koval, et al.

Format adaptive sync signal generator
Patent #: 5339111
Issued on: 08/16/1994
Inventor: Park

Multi-source video synchronization
Patent #: 5517253
Issued on: 05/14/1996
Inventor: De Lange

Video display apparatus for displaying a plurality of video signals having different scanning frequencies and a multi-screen display system using the video display apparatus Patent #: 5557342
Issued on: 09/17/1996
Inventor: Eto, et al.

Inventors

Assignee

Application

No. 129293 filed on 08/05/1998

US Classes:

365/230.01, ADDRESSING348/555, For receiving more than one format at will (e.g., NTSC/PAL)365/230.03Plural blocks or banks

Examiners

Primary: Fears, Terrell W.

Attorney, Agent or Firm

Foreign Patent References

  • 0 279 229 EP. 08/21/1988
  • WO 89/06031 WO. 06/21/1989

International Class

G09G 001/16

Abstract

A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.

Other References

  • K. Suizu, et al., "Emerging Memory Solutions for Graphics Applications," IEICE Transactions on Electronics, vol. E78-c, No. 7, Jul. 1995; pp. 773-78
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