U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Stacked multi-chip modules using C4 interconnect technology having improved thermal management

Patent 6278181 Issued on August 21, 2001. Estimated Expiration Date: Icon_subject June 28, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3787252

Interconnection in multi element planar structures
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Issued on: 07/13/1976
Inventor: Blocker, III

Three-dimensional packaging of focal plane assemblies using ceramic spacers
Patent #: 4956695
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Inventor: Robinson, et al.

Heat pipe type cooling apparatus for semiconductor
Patent #: 4982274
Issued on: 01/01/1991
Inventor: Murase, et al.

Flip substrate for chip mount
Patent #: 5039628
Issued on: 08/13/1991
Inventor: Carey

Three-dimensional multichip module systems
Patent #: 5111278
Issued on: 05/05/1992
Inventor: Eichelberger

Three-dimensional multi-chip pad array carrier
Patent #: 5222014
Issued on: 06/22/1993
Inventor: Lin

Stacking three dimensional leadless multi-chip module and method for making the same
Patent #: 5247423
Issued on: 09/21/1993
Inventor: Lin, et al.

Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
Patent #: 5258648
Issued on: 11/02/1993
Inventor: Lin

Multichip module having a stacked chip arrangement
Patent #: 5323060
Issued on: 06/21/1994
Inventor: Fogal, et al.

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Inventor

Assignee

Application

No. 340419 filed on 06/28/1999

US Classes:

257/712, With provision for cooling the housing or its contents257/701, Insulating material257/778, Flip chip257/E21.511, Mounting on insulating member provided with metallic leads, e.g., flip-chip mounting, conductive die mounting (EPO)257/E23.011, Internal lead connections, e.g., via connections, feedthrough structures (EPO)257/E23.098, By flowing liquids (EPO)257/E25.013, Stacked arrangements of devices (EPO)438/122, Possessing thermal dissipation structure (i.e., heat sink)438/125Insulative housing or support

Examiners

Primary: Wilczewski, Mary
Assistant: Goodwin, David

Attorney, Agent or Firm

International Class

H01L 023/52

Abstract

A flip-chip circuit arrangement having improved thermal management includes a base substrate having a top surface which includes one or more bond pads thereon. The arrangement further includes a semiconductor substrate having circuitry and one or more bond pads thereon, wherein the one or more bond pads on the semiconductor substrate correspond to the one or more bond pads on the base substrate. The semiconductor substrate has one or more channels which extend from a top surface to a bottom surface thereof and the channels facilitate a transfer of heat due to power dissipation of the circuitry away from the semiconductor substrate.

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