Defect gettering by induced stress
June 17, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDielectrically isolated semiconductor devices Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate Method of making complete dielectric isolation structure in semiconductor integrated circuit Trench pillar for wafer processing Method of forming island with polysilicon-filled trench isolation Semiconductor device having a shield which is maintained at a reference potential Method for forming isolated semiconductor structures Method for producing an insulating trench in an SOI substrate SOI (silicon on insulator) substrate with enhanced gettering effects Semiconductor wafer with enhanced pre-process denudation and process-induced gettering InventorsApplicationNo. 334987 filed on 06/17/1999US Classes:438/476, By layers which are coated, contacted, or diffused257/E21.318, Of silicon body, e.g., for gettering (EPO)438/402, And gettering of substrate438/471GETTERING OF SUBSTRATEExaminersPrimary: Meier, Stephen D.Assistant: Brophy, Jamie L. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/322AbstractThe present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5). | |
