Cache memory device
August 7, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCache memory having a variable data block size Adaptive domain partitioning of cache memory space Set associative memory Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses Input/output cache Fast tag compare and bank select in set associative cache Reconfigurable multi-way associative cache memory Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch Method and apparatus for cache miss reduction by simulating cache associativity Patent #: 5442571 InventorAssigneeApplicationNo. 302695 filed on 09/09/1994US Classes:711/118CachingExaminersPrimary: Myers, Paul R.Attorney, Agent or FirmForeign Patent References
International ClassG06F 007/544.4Foreign Application Priority Data1992-03-13 FRAbstractA cache memory device including an input/output (ESRQ) for receiving a request (REQ) having a main address (AP) and optional data (D); an input/output (ESMP) to an addressable main memory (MP) or another addressable cache memory; a plurality of X memory banks (BCi) wherein i is lower than X and higher than 0, each having a number Li of lines for containing data, the lines being individually designated by a local address (AL) in each bank; an arrangement for answering a request (REQ) by connecting the main address (AP) in the request to a local address (AL) in the bank (BCi) in accordance with a predetermined la (fi) for each bank (BCi), whereby the line thus designated in the bank (BCi) is the only line to contain the datum referred to by the main address; and an arrangement (CHA) for loading the cache memory according to the received requests. At least two predetermined laws (fi) are substantially distinct depending on the banks in question, and the two banks in question are addressed separately, hereby the average cache memory data access hit rate is improved.Other References
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