Flash memory structure and method of manufacture
Patent 6255689 Issued on July 3, 2001. Estimated Expiration Date: 
December 20, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 20, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPacking density for flash memories Patent #: 5892257 InventorApplicationNo. 467251 filed on 12/20/1999US Classes:257/314, Variable threshold (e.g., floating gate memory device)257/315, With floating gate electrode257/316, With additional contacted control electrode257/513, Vertical walled groove257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)257/E29.306, Hot carrier injection from channel (EPO)438/201, Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate)438/209, Including additional vertical channel insulated gate field effect transistor438/212, Vertical channel438/221, Dielectric isolation formed by grooving and refilling with dielectric material438/230, Utilizing gate sidewall structure438/694Combined with coating stepExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmInternational ClassH01L 029/72AbstractA flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.Field of SearchVariable threshold (e.g., floating gate memory device)With floating gate electrode With additional contacted control electrode Vertical walled groove Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate) Dielectric isolation formed by grooving and refilling with dielectric material Including additional vertical channel insulated gate field effect transistor Vertical channel Utilizing gate sidewall structure Combined with coating step | |
