Logic module for integrated digital circuits
Dynamic delayed transaction discard counter in a bus bridge of a computer system
Dynamically configurable variable frequency and duty cycle clock and signal generation Patent #: 6040725
ApplicationNo. 09/441323 filed on 11/16/1999
US Classes:327/291, Clock or pulse waveform generating327/294With common output
ExaminersPrimary: Wells, Kenneth B.
Assistant: Nguyen, Hiep T.
Attorney, Agent or Firm
International ClassesH03K 5/22 (20060101)
H03K 5/135 (20060101)
H03K 5/24 (20060101)
AbstractThe present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a "steady-state" condition. After the input signal achieves a "steady-state" condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.