Abstract

A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased. The positive voltage is greater in magnitude than the external primary voltage source and is preferably produced utilizing a charge pump circuit powered by the primary voltage source. The relatively large source voltage enables the cell to be erased rapidly and with a reduced tendency to produce positive charges which can be trapped in the gate oxide intermediate the floating gate and the channel/source of the cell.