Patent ReferencesSystem comprising field programmable gate array and intelligent memory Structure and method for loading RAM data within a programmable logic device Memory in a programmable logic device Byte accessible memory interface using reduced memory control pin count Patent #: 6055594 InventorsAssigneeApplicationNo. 09/283654 filed on 04/01/1999US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)326/38Having details of setting or programming of interconnections or logic functionsExaminersPrimary: Tokar, MichaelAssistant: Le, Don Phu Attorney, Agent or FirmInternational ClassH03K 19/177 (20060101)AbstractAn image processing system uses an FPGA and an external memory to form neighborhoods for image processing. The FPGA is connected to the external memory in a way that reuses address lines, and increases the effective bandwidth of the operation. | |