Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment
July 20, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOrganization of an integrated cache unit for flexible usage in cache system design Methods and apparatus for caching interlock variables in an integrated cache memory Programmable cache memory as well as system incorporating same and method of operating programmable cache memory Cache coherency protocol for multi processor computer system Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand Apparatus and method for optimizing performance of a cache memory in a data processing system Cache system for reducing memory latency times Multiprocessor cache examiner and coherency checker Block buffer for instruction/operand caches System and method for practicing essential inclusion in a multiprocessor and cache hierarchy InventorsApplicationNo. 119310 filed on 07/20/1998US Classes:711/141, Coherency714/42Memory or storage device component faultExaminersPrimary: Verbrugge, KevinAttorney, Agent or FirmForeign Patent References
International ClassG06F 012/00AbstractFor simulation of a multiprocessor system having a multi-level cache hierarchy, possible and legal cache coherency state combinations are classified based on the state of one level one cache, and subclassified within the major classes to define unique combinations, a number significantly less than the number of all possible combinations. For data words in the test case, a cache coherency state combination is randomly selected from a combination table listing all subclasses. Stale data generated by inverting all or part of the original data from the test case may be preloaded with the coherency states as necessary. Existing coherency is maintained when test case data is preloaded to a cache location already preloaded to avoid previously loaded stale data from becoming valid with the new coherency state. Coherency state combinations which are preloaded are tracked to help ensure that all subclasses an are preloaded and tested during simulation prior to tapeout. The cache preload mechanism of the present invention allows bugs which only occur when the caches are in some corner case states to be detected.Other References
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