Patent 6238976 Issued on May 29, 2001. Estimated Expiration Date: February 27, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/259, Including forming gate electrode in trench or recess in substrate257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)438/266Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)
A method of forming a memory array. The method includes forming a plurality of first conductivity type semiconductor pillars upon a substrate. Each pillar has a top and a side surface. The method includes forming a plurality of first source/drain regions, of a second conductivity type. Each of the first source/drain regions formed proximally to an interface between the pillar and the substrate. The method includes forming a plurality of second source/drain regions, of a second conductivity type, each of the second source/drain regions formed within one of the pillars and distal to the substrate and separate from the first/source drain region. A gate dielectric is formed on at least a portion of the side surface of the pillars. At least two floating gates are formed per pillar. Each of the floating gates are formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric, a plurality of control gates are formed substantially adjacent to at least one of the floating gates and insulated therefrom. An intergate dielectric is formed, interposed between ones of the floating gates and ones of the control gates. A plurality of first gate lines are formed such that each first gate line interconnects ones of the control gates. The method includes forming a plurality of second gate lines, each second gate line interconnecting ones of the control gates. At least one first source/drain interconnection line is formed interconnecting ones of the first source/drain regions. And, the method includes forming a plurality of data lines such that each data line interconnects ones of the second/source drain regions.
Other References
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997)
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic Ram's Utilizing The Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625, (Apr. 1992)
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989)
Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 4-7, 1994)
De, V.K., et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996)
Fong, Y., et al., "Oxides Grown on Textured Single-Crystal Silicon--Dependence on Process and Application in EEPROMs ", IEEE Transactinos on Electron Devices, 37, 583-590, (Mar. 1990)
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997)
Gong, S., et al., "Techniques for Reducing Switching Noise in High Speed Digital Systems", Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, 21-24, (1995)
Burnett, D., et al., "Statistical Threshold-Voltage Variatiion and its Impact on Supply-Voltage Scaling", Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995)
Hao, M.Y., et al., "Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon", Appl. Phys. Lett., 60, 445-447, (Jan. 1992)
Harada, M., et al., "Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 96-97, (Jun. 11-13, 1996)
Jun, Y.K., et al., "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications", IEEE Electron Device Letters, 13, 430-432, (Aug. 1992)
Kim, Y.S., et al., "A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum", In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA, 675-680, (1996)
Koshida, N., et al., "Efficient Visible Photoluminescence from Porous Silicon", Japanese Journal of Applied Physics, 30, L1221-L1223, (Jul. 1991)
Lehmann, V., "The Physics of Macropore Formation in Low Doped n-Type Silicon", Journal of the Electrochemical Society, 140(10), 2836-2843, (Oct. 1993)
Pein, H., et al., "A 3-D Sidewall Flash EPROM Cell and Memory Array", IEEE Transactions on Electron Devices, 40, 2126-2127, (Nov. 1993)
Sagara, K., et al., "A 0.72 micro-meter2 Recessed STC (RSTC) Technology for 256Mbit DRAMs using Quarter-Micron Phase-Shift Lithography", 1992 Symposium on VLSI Technology, Digest of Technical Papers, Seattle, WA, 10-11, (Jun. 2-4, 1992)
Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996)
Sherony, M.J., et al., "Reduction of Threshold Voltage Sensitivity in SOI MOSFET's", IEEE Electron Device Letters, 16, 100-102, (Mar. 1995)
Hu, G., et al., "Will Flash Memory Replace Hard Disk Drive?", 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline, 1 p., (Dec. 13, 1994)
Jung, T., et al., "A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications", IEEE Journal of Solid-State Circuits, 31, 1575-1582, (Nov. 1996)
Pein, H., et al., "Performance of the 3-D PENCIL Flash EPROM Cell and Memory Array", IEEE Transactions on Electron Devices, 42, 1982-1991, (Nov., 1995)
Pein, H.B., et al., "Performance of the 3-D Sidewall Flash Eprom Cell", IEEE International Electron Devices Meeting, Technical Digest, 11-14, (1993)
Takato, H., et al., "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", 1988 IEEE International Electron Devices Meeting, Technical Digest, 222-225, (1988)
Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997)
Stellwag, T.B., et al., "A Vertically-Integrated GaAs Biopolar DRAM Cell", IEEE Transactions on Electron Devices, 38, 2704-2705, (Dec. 1991)
Temmler, D., "Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit Drams", 1991 Symposium on VLSI Technology, Digest of Technical Papers, Oiso, 13-14, (May 28-30, 1991)
Wang, P.W., et al., "Excellent Emission Characteristics of Tunneling Oxides Formed Using Ultrathin Silicon Films for Flash Memory Devices", Japanese Journal of Applied Physics, 35, 3369-3373, (Jun. 1996)
Watanabe, H., et al., "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs", 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, 17-18, (1993)
Watanabe, H., et al., "An Advanced Fabrication Technology of Hemispherical Graines (HSG) Poly-Si for High Capacitance Storage Electrodes", Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Japan, 478-480, (1991)
Watanabe, H., et al., "Device Application and Structure Observation for Hemispherical-Grained Si", J. Appl. Phys., 71, 3538-3543, (Apr. 1992)
Watanabe, H., et al., "Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Method", Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan, 422-424, (1992)
Yoshikawa, K., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 240-241, (Jun. 11-13, 1996)
February 27, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
