U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Coprocessor interface having pending instructions queue and clean-up queue and dynamically allocating memory

Patent 6237079 Issued on May 22, 2001. Estimated Expiration Date: Icon_subject February 18, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Address translation systems for high speed computer memories
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More ...

Inventor

Assignee

Application

No. 025758 filed on 02/18/1998

US Classes:

712/34, Including coprocessor711/153Shared memory partitioning

Examiners

Primary: Follansbee, John

Attorney, Agent or Firm

Foreign Patent References

  • 00863380 EP. 08/13/1983
  • 0115179 EP. 08/13/1984
  • 0150060 EP. 07/13/1985
  • 0154341 EP. 09/13/1985
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  • 0272705 EP. 06/13/1986
  • 0184547 EP. 06/13/1986
  • 0205712 EP. 12/13/1986
  • 0206892 EP. 12/13/1986
  • 0218287 EP. 04/13/1987
  • 0254824 EP. 02/13/1988
  • 0275979 EP. 07/13/1988
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  • 0286183 EP. 10/13/1988
  • 0311034 EP. 04/13/1989
  • 0335990 EP. 10/13/1989
  • 0335306 EP. 10/13/1989
  • 0343992 EP. 11/13/1989
  • 0348703 EP. 01/13/1990
  • 0360155 EP. 03/13/1990
  • 0380720 EP. 08/13/1990
  • 0383678 EP. 08/13/1990
  • 0472961 EP. 03/13/1992
  • 0482864 EP. 04/13/1992
  • 0486154 EP. 05/13/1992
  • 0506111 EP. 09/13/1992
  • 0523764 EP. 01/13/1993
  • 0525749 EP. 02/13/1993
  • 0535893 EP. 04/13/1993
  • 0589682 EP. 03/13/1994
  • 0588726 EP 03/13/1994
  • 0593046 EP. 04/13/1994
  • 0600112 EP. 06/13/1994
  • 0612007 EP. 08/13/1994
  • 0623799 EP. 11/13/1994
  • 0626661 EP. 11/13/1994
  • 0655712 EP. 05/13/1995
  • 0655854 EP. 05/13/1995
  • 0660247 EP. 06/13/1995
  • 0674266 EP. 06/13/1995
  • 0675632 EP. 10/13/1995
  • 0692913 EP. 01/13/1996
  • 0708563 EP. 04/13/1996
  • 0714166 EP. 05/13/1996
  • 0720104 EP. 07/13/1996

International Class

G06F 015/00

Foreign Application Priority Data

1997-03-30 AU

Abstract

The present invention discloses a method of controlling the interaction of a host CPU (202) and at least one co-processor (224) in a computer system (201) to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions. The co-processor instructions to be executed, and those which have been executed are allocated to respective queues (1040, 1041). From time to time the latter queue (1041) is cleaned up under control of the CPU (202) to release memory resources previously allocated to the co-processor by the CPU. This dynamic memory management arrangement preferably includes an instruction generator (1030), a memory manager (1031) and a queue manager (1032).

Other References

  • Arai et al., "A Fast DCT-SQ Scheme for Images," Trans. IEICE, vol. E 71, no. 11, 11/88 pp. 1095-109
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