Method and system for emitter partitioning for SiGe RF power transistors
November 12, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh frequency bipolar transistor structures Inverted groove isolation technique for merging dielectrically isolated semiconductor devices Magnetically sensitive semiconductor device Integrated circuit having a lateral multicollector transistor Integrated multicellular transistor chip for power switching applications Transistors with emitters having at least three sides Method for manufacturing an offset lattice bipolar transistor Segmented emitter low noise transistor Patent #: 5723897 InventorsAssigneeApplicationNo. 189804 filed on 11/12/1998US Classes:257/197, Bipolar transistor257/560, With multiple collectors or emitters257/563, With multiple separately connected emitter, collector, or base regions in same transistor structure257/578, With enlarged emitter area (e.g., power device)257/579, With separate emitter areas connected in parallel257/580, With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means)257/E29.032, Noninterconnected multiemitter structures (EPO)257/E29.193, Comprising lattice mismatched active layers (e.g., SiGe strained layer transistors) (EPO)438/312, Having heterojunction438/342Having multiple emitter or collector structureExaminersPrimary: Mintel, WilliamAttorney, Agent or FirmInternational ClassesH01L 027/082H01L 027/102 H01L 029/70 H01L 031/11 AbstractA power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.Other References
Field of SearchWith multiple collectors or emittersWith separate emitter areas connected in parallel With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means) With enlarged emitter area (e.g., power device) Bipolar transistor With multiple separately connected emitter, collector, or base regions in same transistor structure Having multiple emitter or collector structure Having heterojunction | |
