Patent ReferencesStage apparatus in exposing apparatus Projection exposure apparatus Method and apparatus for exposure process Optical focus phase shift test pattern, monitoring system and process Positioning method and apparatus Alignment method Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate Edge overlay measurement target for sub-0.5 micron ground rules Method and system for measurement of resist pattern Patent #: 5783342 InventorAssigneeApplicationNo. 916337 filed on 08/22/1997US Classes:700/121, Integrated circuit production or semiconductor fabrication716/21Pattern exposureExaminersPrimary: Gordon, Paul P.Attorney, Agent or FirmInternational ClassG06F 019/00Foreign Application Priority Data1996-08-23 JPAbstractA method of measuring the overlay offset of a resist pattern formed on a semiconductor wafer is disclosed. An aligner outputs wafer-by-wafer measured alignment data. A scattering of the wafer-by-wafer alignment data is calculated. If the scattering is greater than a preselected value, all the wafers of a lot brought to a measuring step are tested. If the scattering is smaller than the preselected value, only sample wafers are tested. Whether or not sampling should be effected is automatically determined.Field of SearchIntegrated circuit production or semiconductor fabricationDESIGN OF SEMICONDUCTOR MASK Mesh generation Pattern exposure MEANS TO ALIGN OR POSITION AN OBJECT RELATIVE TO A SOURCE OR DETECTOR Irradiation of semiconductor devices Ion bombardment Pattern control With registration indicia (e.g., scale) Radiation sensitive composition or product or process of making Light scattering or refractive index image formation Making electrical device PLURAL EXPOSURE STEPS | |