Method of forming a semiconductor diode with depleted polysilicon gate structure

Patent 6232163 Issued on May 15, 2001. Estimated Expiration Date:

July 28, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Application

No. 362549 filed on 07/28/1999

US Classes:

438/212, Vertical channel257/E27.05, Metal-insulated-semiconductor (MIS) diode (EPO)257/E29.195, Gated diode structure (EPO)438/268Vertical channel

Examiners

Primary: Chaudhuri, Olik
Assistant: Pham, Hoa Q.

Attorney, Agent or Firm

McGuireWoods, LLP, Shkurko, Esq.; Eugene I.

Foreign Patent References

401185971 JP. 07/20/1989

International Class

H01L 021/823.8

Abstract

A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.