Vertical gate transistors in pass transistor logic decode circuits
Patent 6222788 Issued on April 24, 2001. Estimated Expiration Date: 
May 30, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 30, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVertical DRAM cell and method Decoder circuit having selective transfer circuit for decoded output signal Multimedia storage system with highly compact memory device Vertically formed neuron transister having a floating gate and a control gate Dense vertical programmable read only memory cell structures and processes for making them Programmable memory address decode array with vertical transistors Patent #: 5991225 InventorsApplicationNo. 580860 filed on 05/30/2000US Classes:365/230.06, Particular decoder or driver circuit257/302, Vertical transistor257/315, With floating gate electrode257/E21.621, With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)257/E21.625, With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)257/E29.264With multiple gate structure (EPO)ExaminersPrimary: Nguyen, Tan T.Attorney, Agent or FirmInternational ClassG11C 008/00AbstractSystems and methods are provided for vertical gate transistors in static pass transistor decode circuits. The vertical gate transistors have multiple vertical gates which are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel decode circuits of the present invention include an address decoder for a memory device. The decode circuit includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number logic cells that disposed at the intersections of output lines and address lines. According to the teachings of the present invention each logic cell includes a source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.Other References
Field of SearchParticular decoder or driver circuitMultiplexing Particular connection Extended floating gate Variable threshold (e.g., floating gate memory device) With floating gate electrode With additional contacted control electrode With irregularities on electrode to facilitate charging or discharging of floating electrode Additional control electrode is doped region in semiconductor substrate Vertical transistor | |
