Symmetric filtering based VLSI architecture for image compression
Patent 6215908 Issued on April 10, 2001. Estimated Expiration Date: 
February 24, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 24, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesElectronic image processing circuit Progressive sub-band image coding system System and method for implementing the fast wavelet transform Method and apparatus for minimally-shifted wavelet decomposition and recomposition Overlapped reversible transforms for unified lossless/lossy compression Patent #: 5999656 InventorsAssigneeApplicationNo. 258118 filed on 02/24/1999US Classes:382/240, Pyramid, hierarchy, or tree structure375/240.19, Wavelet382/263, Highpass filter (i.e., for sharpening or enhancing details)382/264Lowpass filter (i.e., for blurring or smoothing)ExaminersPrimary: Au, AmeliaAssistant: Johnson, Timothy M. Attorney, Agent or FirmInternational ClassesG06K 009/36G06K 009/46 AbstractAn apparatus to perform symmetric filtering image compression is provided. The apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image. The apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs. The apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs. Additionally, the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits. The apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits.Other References
Field of SearchTree structureParallel processors (e.g., identical processors) Using separate coders for different picture features (e.g., highs, lows) Subband encoding (e.g., low horizontal/low vertical frequency, low horizontal/high vertical frequency) Involving transform coding Transformed sample selection (e.g., hierarchical sample selection) Individual processing of different parts of image frequency band (e.g., sum and difference, high band/low band) Individual processing of different parts of image frequency band (e.g., sum and difference, high band/low band) Separate coders Subband coding Transform Wavelet IMAGE COMPRESSION OR CODING Parallel coding architecture Pyramid, hierarchy, or tree structure Transform coding Image filter Multilayered image transformations Pipeline processing Parallel processing Highpass filter (i.e., for sharpening or enhancing details) Lowpass filter (i.e., for blurring or smoothing) Multidimensional data Transform Multidimensional Pipeline Systolic | |
