Low temperature deposition of barrier layers
September 3, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDynamic random access memory having stacked capacitor structure Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same Process for fabricating ferroelectric integrated circuit Hybrid metal/metal oxide electrodes for ferroelectric capacitors Ferroelectric integrated circuit High-dielectric-constant material electrodes comprising thin platinum layers High-dielectric-constant material electrodes comprising thin platinum layers Method of manufacturing semiconductor devices Method of forming a charge-storage electrode of semiconductor device InventorApplicationNo. 146300 filed on 09/03/1998US Classes:438/653, At least one layer forms a diffusion barrier257/295, With ferroelectric material layer257/E21.584, Barrier, adhesion or liner layer (EPO)427/60, Post-treating with solid treating member438/458, Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.)438/600Using structure alterable to conductive state (i.e., antifuse)ExaminersPrimary: Elms, RichardAssistant: Luy, Pho Attorney, Agent or FirmInternational ClassH01L 021/44AbstractThe present invention provides a method for forming a barrier layer, preferably a conductive barrier layer. According to the present invention, a barrier layer is formed from an organometallic precursor in the presence of an oxidant in a low temperature deposition technique using a platinum containing precursor. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.Other References
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