Silicon-on-insulator islands and method for their formation
August 7, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of forming lateral bipolar transistors Process for producing NPN type lateral transistor with minimal substrate operation interference Method of producing integrated silicon structures on isolated islets of the substrate PNP-type lateral transistor with minimal substrate operation interference and method for producing same Method of manufacturing isolated semiconductor devices Method of fabricating semiconductor device Trench isolation method having a double polysilicon gate formed on mesas Method of producing a thin silicon-on-insulator layer Method for producing an insulating trench in an SOI substrate Sixteen megabit static random access memory (SRAM) cell InventorApplicationNo. 130989 filed on 08/07/1998US Classes:438/412, Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.)257/254, Physical deformation (e.g., strain sensor, acoustic wave detector)257/E21.564, SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)438/52, Having cantilever element438/404, Total dielectric isolation438/405And separate partially isolated semiconductor regionsExaminersPrimary: Chaudhari, ChandraAssistant: Blum, David S Attorney, Agent or FirmInternational ClassH01L 021/76AbstractSilicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.Other References
Field of SearchTotal dielectric isolationResponsive to corpuscular radiation (e.g., nuclear particle detector, etc.) Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.) Having cantilever element And separate partially isolated semiconductor regions Encroachment of separate locally oxidized regions Plural doping steps Physical deformation (e.g., strain sensor, acoustic wave detector) | |
