Solid state imaging apparatus for imaging a two dimensional optical image having a number of integration circuits
November 27, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesA/D photodiode signal conversion apparatus Read-out circuit for a photodetector High temperature photodetector array Staring IR-FPA with on-FPA adaptive dynamic range control electronics Imaging device having reduced vertical crosstalk Fast scan reset for a large area x-ray detector Image sensor comprising a two-dimensional array of photodetectors with both column and row output circuits which are in parallel Solid-state imaging apparatus Patent #: 5731578 InventorAssigneeApplicationNo. 757423 filed on 11/27/1996US Classes:348/308, Including switching transistor and photocell at each pixel site (e.g., "MOS-type" image sensor)250/208.1, Plural photosensitive image detecting element arrays348/310, With diode in series with photocell348/315With staggered or irregular photosites or specified channel configurationExaminersPrimary: Garber, Wendy R.Assistant: Vu, Ngoc-Yen Attorney, Agent or FirmForeign Patent References
International ClassH04N 003/14AbstractIn a solid-state imaging apparatus of the present invention, after an integration operation is started with an integration circuit by setting a reset instruction signal at logical zero, charges stored in a light receiving device are discharged by selecting this light receiving device. A value of an integration signal obtained by an integration operation of an integration circuit is compared with a reference value by a comparing circuit. A capacitance control section informs a capacitance instruction signal to a variable capacitor section of the integration circuit in response to a comparing result. A feedback loop is formed, which consists of the integration circuit, the comparing circuit, and a capacitance control circuit. When the value of the integration signal agrees finally with the reference value within resolution, the capacitance control section outputs a value in accordance with the capacitance instruction signal. This value is sequentially read out through a horizontal reading-out section.Other References
Field of SearchPlural photosensitive image detecting element arraysSolid-state image sensor With amplifier Pixel amplifiers X - Y architecture With charge transfer type output register With charge transfer type selecting register Photosensitive switching transistors or "static induction" transistors Including switching transistor and photocell at each pixel site (e.g., "MOS-type" image sensor) Exclusively passive light responsive elements in the matrix With diode in series with photocell Charge-coupled architecture With staggered or irregular photosites or specified channel configuration Charges transferred to opposed registers Field or frame transfer type Charges alternately switched from vertical registers into separate storage registers; or having vertical transfer gates Interline readout Using multiple output registers Interline readout Using multiple output registers | |
