U.S. patents available from 1976 to present.
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Boosted sensing ground circuit

Patent 6198677 Issued on March 6, 2001. Estimated Expiration Date: Icon_subject December 29, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Sensing circuit for semiconductor memory with limited bitline voltage swing
Patent #: 5257232
Issued on: 10/26/1993
Inventor: Dhong, et al.

Semiconductor memory device
Patent #: 5508965
Issued on: 04/16/1996
Inventor: Nomura, et al.

Semiconductor memory device
Patent #: 5619465
Issued on: 04/08/1997
Inventor: Nomura, et al.

Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device
Patent #: 5646900
Issued on: 07/08/1997
Inventor: Tsukude, et al.

Memory device with current limiting feature Patent #: 5949729
Issued on: 09/07/1999
Inventor: Suyama, et al.

Inventors

Application

No. 221629 filed on 12/29/1998

US Classes:

365/203, Precharge365/207Differential sensing

Examiners

Primary: Dinh, Son T.

Attorney, Agent or Firm

International Class

G11C 007/00

Abstract

A new noise control circuit which connects the sense ground node to ground in two specific period of times so that the NSA bouncing is minimized. Preferably these two periods are at the beginning of setting the n-type latch and when the data is transferring and CSL is switching. A pulse of NSET and together with whole CSLEN signal are used to activate the noise control circuit. The noise control circuit can also include a n-FET diode with its gate connected to the source and its drain tied to the Vbleq power supply. It is more preferable to use a low threshold voltage of n-FET device with Vt at 0.55 volts to form the clamp diode.

Other References

  • Tsukasa Ooishi, et al., "An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's," IEEE Journal of Solid-State Circuits, vol. 30, No. 4 (Apr. 1995)
  • Takahiro Tsuruda, et al. "High-Speed/High-Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI's," IEEE Journal of Solid-State Circuits, vol. 32, No. 3 (Mar. 1997
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