Semiconductor memory device with reduced power consumption and stable operation in data holding state
December 6, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode Semiconductor memory device having controllable supplying capability of internal voltage Maintaining data integrity in DRAM while varying operating voltages Semiconductor memory device and memory system Dynamic semiconductor memory device with SOI structure and body refresh circuitry Semiconductor memory device having controllable supplying capability of internal voltage DRAM with reduced electric power consumption Semiconductor memory device Semiconductor memory device with reduced power consumption and stable operation in data holding state Patent #: 6026043 InventorApplicationNo. 455461 filed on 12/06/1999US Classes:365/222, Data refresh365/185.22, Verify signal365/189.09, Including reference or bias voltage generator365/189.11, Including level shift or pull-up circuit365/204Accelerating charge or dischargeExaminersPrimary: Nguyen, Viet Q.Attorney, Agent or FirmForeign Patent References
International ClassG11C 011/24Foreign Application Priority Data1997-09-16 JPAbstractThe semiconductor memory device has a normal operation mode and a self-refresh mode, and includes a VBB generation circuit generating a first substrate voltage when an internal power supply voltage is larger than a predetermined value and a second substrate voltage of an absolute value smaller than that of the first substrate voltage when VCC is smaller than the predetermined value, a bit line equivalent voltage generation circuit outputting voltage VCC /2 produced by resistive dividing when internal power supply voltage is lower than the predetermined value in self-refresh mode, a 4KE signal generation circuit generating a signal for performing a 4K operation in the self-refresh mode when internal power supply voltage is lower than the predetermined value and a refresh address generation circuit. | |
