Conditional branch control method
June 29, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processor having branch predicting function Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware Instruction cache memory apparatus with advanced read function that predicts whether to read out a next instruction block including an address register, a counter and a selector Digital data processing system including efficient arrangement to support branching within trap shadows Address generating device for memory tester Patent #: 6019501 InventorAssigneeApplicationNo. 106083 filed on 06/29/1998US Classes:712/239, Branch prediction712/215, Simultaneous issuance of multiple instructions712/238, Branch target buffer714/718Memory testingExaminersPrimary: Pan, Daniel H.Assistant: Chen, Te Yu Attorney, Agent or FirmForeign Patent References
International ClassesG06F 009/42G06F 009/38 G11C 007/08 Foreign Application Priority Data1997-07-02 JPAbstractIn order to effectively reduce branch hazards without a restriction to a structure of a pipeline, the contents of instructions and the like during control of conditional branching in an information processing apparatus which processes an instruction by pipeline processing, before a condition of a conditional branch instruction becomes defined, that is, before a branch judgement is made, pipeline information of a subsequent instruction which is subsequent to the conditional branch instruction is saved so that an instruction beyond a branch is fed to a pipeline in advance. When the condition is met, the instruction beyond the branch is executed as it directly is. When the condition is not met, the saved pipeline information of the subsequent instruction is returned to the pipeline and the subsequent instruction which is subsequent to the conditional branch instruction is executed.Other References
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