Design verification method for programmable logic design
January 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSimulator system for logic design validation Programmable digital signal testing system Logic simulator using small capacity memories for storing logic states, connection patterns, and logic functions Circuit simulation method with clock event suppression for debugging LSI circuits Knowledge based method and apparatus for designing integrated circuits using functional specifications Logic circuit simulation method Static timing analysis of semiconductor digital circuits Computer apparatus and method for logical modelling Integrated electric design system with automatic constraint satisfaction Layout pattern generation and geometric processing system for LSI circuits InventorApplicationNo. 227293 filed on 04/13/1994US Classes:702/117, Of circuit324/76.11MEASURING, TESTING, OR SENSING ELECTRICITY, PER SEExaminersPrimary: Cuchlinski, William A. Jr.Attorney, Agent or FirmInternational ClassG01R 031/14AbstractA technique for checking a logic design for compliance with a set of design rules in a computer-aided logic design system. An initial logic design is provided in computer-readable form in a logic design file. A set of design rules expressing permitted and prohibited structural and functional logic device relationships is provided as a portion of a logic design simulation system capable of synthesizing the initial design into a simulated network list. The initial design is checked against the various design rules incorporated into the set, and any violation of the design rules by the initial logic design is visibly displayed to the user. In one mode of operation, a list of user selectable optional rules is visibly displayed. A hierarchy of levels of design compliance is also displayed for user selection. For some design rules, a comparison can be made with the synthesized version of the initial logic design in order to spot design rule violations introduced by the synthesis process.Other References
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