Method and system for determining critical area for circuit layouts using voronoi diagrams
Patent 6178539 Issued on January 23, 2001. Estimated Expiration Date: September 17, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
716/7, Partitioning (e.g., function block, ordering constraint)257/E21.525, Procedures, i.e., sequence of activities consisting of plurality of measurement and correction, marking or sorting steps (EPO)716/2, Optimization (e.g., redundancy, compaction)716/4, Testing or evaluating716/11Layout editor (e.g., updating)
A method for computing critical area for shorts of a layout, in accordance with the present invention, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for shorts in the layout. A system is also provided for calculating the critical area.
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September 17, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
