Reducing timing variance of signals from an electronic device
December 31, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3843930 Multiple phase clock generator Digital signal delay circuit Triggered frequency locked oscillator having programmable delay circuit Triggered voltage controlled oscillator using fast recovery gate High order digital phase-locked loop system Phase-locked loop delay line High speed clock distribution system Integrated logic circuit with clock skew adjusters Clock generation InventorsApplicationNo. 002019 filed on 12/31/1997US Classes:713/401, Using delay713/500CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSISExaminersPrimary: Heckler, Thomas M.Attorney, Agent or FirmInternational ClassG06F 001/04AbstractA time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.Other References
Field of SearchSYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSESUsing delay CLOCK, PULSE, OR TIMING SIGNAL GENERATION OR ANALYSIS Correction for skew, phase, or rate Synchronizing Having specific delay in producing output waveform Including significant compensation (e.g., temperature compensated delay, etc.) Including delay line or charge transfer device Clock or pulse waveform generating | |
