Technique for producing small islands of silicon on insulator
Patent 6174784 Issued on January 16, 2001. Estimated Expiration Date: November 14, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/405, And separate partially isolated semiconductor regions257/E21.554, Using auxiliary pillars in recessed region, e.g., to form LOCOS over extended areas (EPO)257/E21.561, Using semiconductor or insulator technology, i.e., SOI technology (EPO)257/E21.564, SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)438/404, Total dielectric isolation438/410, Encroachment of separate locally oxidized regions438/425Combined with formation of recessed oxide by localized oxidation
Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).
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November 14, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
