U.S. patents available from 1976 to present.
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200 Mbps PHY/MAC apparatus and method

Patent 6169729 Issued on January 2, 2001. Estimated Expiration Date: Icon_subject April 8, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Auto negotiation system for a communications network
Patent #: 5610903
Issued on: 03/11/1997
Inventor: Crayford

Full duplex flow control for ethernet networks
Patent #: 5784559
Issued on: 07/21/1998
Inventor: Frazier, et al.

Method and apparatus for switching between full-duplex and half-duplex CSMA/CD systems Patent #: 5825755
Issued on: 10/20/1998
Inventor: Thompson, et al.

Inventor

Assignee

Application

No. 833661 filed on 04/08/1997

US Classes:

370/296, Convertible to half duplex370/352Combined circuit switching and packet switching

Examiners

Primary: Martin-Wallace, Valencia
Assistant: Nguyen, Khiem

Attorney, Agent or Firm

International Class

H04L 005/16

Abstract

A 200 Mbps PHY/MAC combination for providing full duplex operation at 400 Mbps is disclosed. The PHY/MAC uses all 4 pairs of wire to create a single channel. A transmit and receive port of a physical layer device is connected to a first end of four pairs of category 5 wiring. A media access control entity sources PLS primitives to manage the flow of frames eight bits a nibble to and from the four pairs of category 5 wiring through the physical layer device. A switch is provided for trunking the four pair of category 5 wiring into a single channel comprising separate 200 Mbps throughput transmit and receive data paths to the physical layer device or into two channels comprising separate 100 Mbps throughput transmit and receive data paths to the physical layer device comprising separate 100 Mbps throughput transmit and receive data paths to the physical layer device. The medium independent interface includes means for providing an eight bit wide transmit data path from the media access control entity to the T2 physical layer device, means for providing an eight bit wide receive data path from the physical layer device to the media access control entity and means for mapping PLS primitives from the media access control entity to the eight bit wide transmit and receive data paths. The eight bit wide transmit and receive data paths of the media independent interface are clocked at 25 MHz, thereby each providing a 200 Mbps data path between the medium access control layer and the physical layer device.

Other References

  • H.W. Johnson, "Fast Ethernet. Dawn of a New Network," 1966, Prentice Hall PTR, USA., pp. 41-52 and 115-125
  • A. Chiang: "Two-Pair Category 3 UTP transceivers for Fast Ethernet," SPIE Emerging High-Speed Local-Area Networks and Wide-Area Networks, Oct. 1995, PA, USA vol. 2608, pp. 20-28
  • Copy of International Search Report cited in corresponding PCT application No. PCT/US98/0727
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