Heat removal from SOI devices by using metal substrates
October 25, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesThermal expansion compensated metal lead frame for integrated circuit package Semiconductor device using insulation coated metal substrate Method of producing a thin silicon-on-insulator layer Edge-heat-sink technique for zone melting recrystallization of semiconductor-on-insulator films Method of packaging a power semiconductor device Insulated-gate semiconductor device with a buried insulation layer SOI by large angle oxygen implant Method of making transistor with oxygen implanted region High thermal conductive silicon nitride sintered body, method of producing the same and press-contacted body Highly thermally conductive interconnect structure for intergrated circuits InventorAssigneeApplicationNo. 426339 filed on 10/25/1999US Classes:257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/508, With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer)257/677, Of specified material other than copper (e.g., Kovar (T.M.))257/E21.567, Using bonding technique (EPO)257/E23.106, Laminates or multilayers, e.g., direct bond copper ceramic substrates (EPO)257/E23.109, Metallic materials (EPO)257/E29.295, Characterized by insulating substrate or support (EPO)438/455, BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES438/459Thinning of semiconductor substrateExaminersPrimary: Smith, MatthewAssistant: Malsawma, Lex H. Attorney, Agent or FirmInternational ClassesH01L 027/01H01L 029/00 H01L 023/495 H01L 021/30 AbstractIn one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate involving providing a metal wafer; forming a low melting point oxide layer over the metal wafer; forming a first insulation layer over the low melting point oxide layer to provide a first structure; providing a second structure comprising a silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer forming a buried insulation layer; and removing a portion of the silicon layer thereby providing the silicon-on-insulator substrate comprising a silicon device layer, the buried insulation layer, the low melting point oxide layer, and the metal wafer.Field of SearchSingle crystal semiconductor layer on insulating substrate (SOI)With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate Substrate is single crystal insulator (e.g., sapphire or spinel) Temperature With means to reduce temperature sensitivity (e.g., reduction of temperature sensitivity of junction breakdown voltage by using a compensating element) Including dielectric isolation means With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer) Of specified material other than copper (e.g., Kovar (T.M.)) With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer THERMOELECTRIC (E.G., PELTIER EFFECT) COOLING BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES Thinning of semiconductor substrate On insulating substrate or layer Bonding of plural semiconductive substrates Combined with the removal of material by nonchemical means Multiple layers Layers formed of diverse composition or by diverse coating processes Compound semiconductor substrate | |
