Transistor with low resistance tip and method of fabrication in a CMOS process
Patent 6165826 Issued on December 26, 2000. Estimated Expiration Date: December 29, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/231, Plural doping steps257/E21.148, From or through or into an applied layer, e.g., photoresist, nitride (EPO)257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)257/E21.635, With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E29.155, Multiple silicon layers257/E29.267, With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO)438/226, With epitaxial semiconductor layer formation438/232, Plural doping steps438/233, And contact formation438/305, Plural doping steps438/306, Plural doping steps438/558, From solid dopant source in contact with semiconductor region438/561, Dopant source within trench or groove438/576, Into grooved or recessed semiconductor region438/586, Combined with formation of ohmic contact to semiconductor region438/589, Recessed into semiconductor substrate438/664Forming silicide
H01L 021/823.8 558 565 581 583 FOR 168 FOR 180 FOR 197 FOR 216 FOR 217 FOR 218 FOR 251 FOR 250 FOR 219
Abstract
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.
December 29, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
