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...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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US Patent 6165826 - Transistor with low resistance tip and method of fabrication in a CMOS process
US Patent Issued on December 26, 2000
Estimated Patent Expiration Date:
December 29, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
December 29, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses. | InventorsApplicationNo. 581243 filed on 12/29/1995US Classes:438/231, Plural doping steps257/E21.148, From or through or into an applied layer, e.g., photoresist, nitride (EPO)257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)257/E21.635, With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E29.155, Multiple silicon layers257/E29.267, With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO)438/226, With epitaxial semiconductor layer formation438/232, Plural doping steps438/233, And contact formation438/305, Plural doping steps438/306, Plural doping steps438/558, From solid dopant source in contact with semiconductor region438/561, Dopant source within trench or groove438/576, Into grooved or recessed semiconductor region438/586, Combined with formation of ohmic contact to semiconductor region438/589, Recessed into semiconductor substrate438/664Forming silicideField of Search438/618, Contacting multiple semiconductive regions (i.e., interconnects)438/620, Forming contacts of differing depths into semiconductor substrate438/639, Having viahole with sidewall component438/640, Having viahole of tapered shape438/652, Plural layered electrode or conductor438/655, Silicide438/648, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/627, At least one layer forms a diffusion barrier438/656, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/598, Selectively interconnecting (e.g., customization, wafer scale integration, etc.)438/638, Having viaholes of diverse width438/645, Having planarization step438/649, Silicide438/600, Using structure alterable to conductive state (i.e., antifuse)438/604, III-V compound semiconductor438/590, Compound semiconductor438/658, Altering composition of conductor438/633, Simultaneously by chemical and mechanical means438/592, Possessing plural conductive layers (e.g., polycide)438/654, Having adhesion promoting layer438/608, Oxidic conductor (e.g., indium tin oxide, etc.)438/609, Transparent conductor438/622, Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)438/657, Having electrically conductive polysilicon component438/653, At least one layer forms a diffusion barrier438/629, Diverse conductive layers limited to viahole/plug438/637, With formation of opening (i.e., viahole) in insulative layer438/626, Planarization438/643, At least one layer forms a diffusion barrier438/660, Including heat treatment of conductive layer438/623, Including organic insulating material between metal levels438/615, Including fusion of conductor438/594, Tunnelling dielectric layer438/612, Forming solder contact or bonding pad438/613, Bump electrode438/619, Air bridge structure438/651, Silicide438/641, Selective deposition438/662, Utilizing laser438/605, Multilayer electrode438/599, With electrical circuit layout438/614, Plural conductive layers438/621, Contacting diversely doped semiconductive regions (e.g., p-type and n-type regions, etc.)438/647, Having electrically conductive polysilicon component438/601, Using structure alterable to nonconductive state (i.e., fuse)438/595, Having sidewall structure438/589, Recessed into semiconductor substrate438/659, Implantation of ion into conductor438/624, Separating insulating layer is laminate or composite of plural insulating materials438/625, At least one metallization level formed of diverse conductive layers438/617, By wire bonding438/631, Having planarization step438/591, Gate insulator structure constructed of plural layers or nonsilicon containing compound438/628, Having adhesion promoting layer438/634, Utilizing etch-stop layer438/610, Conductive macromolecular conductor (including metal powder filled composition)438/611, Beam lead formation438/635, Insulator formed by reaction with conductor (e.g., oxidation, etc.)438/606, Ga and As containing semiconductor438/661, Subsequent fusing conductive layer438/616, By transcription from auxiliary substrate438/607, With epitaxial conductor formation438/602, To compound semiconductor438/630, Silicide formation438/603, II-VI compound semiconductor438/593, Separated by insulator (i.e., floating gate)438/596, Portion of sidewall structure is conductive438/597, To form ohmic contact to semiconductive material438/663, Rapid thermal anneal438/636, Including use of antireflective layer438/644, Having adhesion promoting layer438/632, Utilizing reflow438/650, Having noble group metal (i.e., silver (Ag), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), or alloy thereof)438/646, Utilizing reflow438/642, Diverse conductors438/664, Forming silicide438/191, Having heterojunction438/229, Self-aligned438/230, Utilizing gate sidewall structure438/231, Plural doping steps438/232, Plural doping steps438/259, Including forming gate electrode in trench or recess in substrate438/270, Gate electrode in trench or recess in semiconductor substrate438/330, Resistor438/301, Source or drain doping438/303, Utilizing gate sidewall structure438/305, Plural doping steps438/306, Plural doping steps438/586, Combined with formation of ohmic contact to semiconductor region438/576, Into grooved or recessed semiconductor region257/288, Having insulated electrode (e.g., MOSFET, MOS diode)257/900MOSFET TYPE GATE SIDEWALL INSULATING SPACERExaminersPrimary: Pham, LongAttorney, Agent or FirmUS Patent References4133704, Method of forming diodes by amorphous implantations and concurrent annealing, monocrystalline reconversion and oxide passivation in <100> N-type siliconIssued on: 01/09/1979 Inventor: MacIver , et al.4683645, Process of fabricating MOS devices having shallow source and drain junctions Issued on: 08/04/1987 Inventor: Naguib , et al.4876213, Salicided source/drain structure Issued on: 10/24/1989 Inventor: Pfiester4998150, Raised source/drain transistor Issued on: 03/05/1991 Inventor: Rodder, et al.5006476, Transistor manufacturing process using three-step base doping Issued on: 04/09/1991 Inventor: De Jong, et al.5162263, Semiconductor device having salicide structure, method of manufacturing the same, and heating apparatus Issued on: 11/10/1992 Inventor: Kunishima, et al.5168072, Method of fabricating an high-performance insulated-gate field-effect transistor Issued on: 12/01/1992 Inventor: Moslehi5231042, Formation of silicide contacts using a sidewall oxide process Issued on: 07/27/1993 Inventor: Ilderem, et al.5285088, High electron mobility transistor Issued on: 02/08/1994 Inventor: Sato, et al.5336903, Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures Issued on: 08/09/1994 Inventor: Ozturk, et al.5341014, Semiconductor device and a method of fabricating the same Issued on: 08/23/1994 Inventor: Fujii, et al.5352631, Method for forming a transistor having silicided regions Issued on: 10/04/1994 Inventor: Sitaram, et al.5393685, Peeling free metal silicide films using rapid thermal anneal Issued on: 02/28/1995 Inventor: Yoo, et al.5397909, High-performance insulated-gate field-effect transistor Issued on: 03/14/1995 Inventor: Moslehi5405795, Method of forming a SOI transistor having a self-aligned body contact Issued on: 04/11/1995 Inventor: Beyer, et al.5478776, Process for fabricating integrated circuit containing shallow junction using dopant source containing organic polymer or ammonium silicate Issued on: 12/26/1995 Inventor: Luftman, et al.5538909, Method of making a shallow trench large-angle-tilt implanted drain device Issued on: 07/23/1996 Inventor: Hsu5569624, Method for shallow junction formation Issued on: 10/29/1996 Inventor: Weiner5620912, Method of manufacturing a semiconductor device using a spacer Issued on: 04/15/1997 Inventor: Hwang, et al.5710450, Transistor with ultra shallow tip and method of fabrication Issued on: 01/20/1998 Inventor: Chau, et al.5726071, Manufacturing method of CMOS transistor Issued on: 03/10/1998 Inventor: Segawa, et al.5770507Method for forming a gate-side air-gap structure in a salicide process Issued on: 06/23/1998 Inventor: Chen, et al. Foreign Patent References
International ClassesH01L 021/823.8558 565 581 583 FOR 168 FOR 180 FOR 197 FOR 216 FOR 217 FOR 218 FOR 251 FOR 250 FOR 219 |
