Output buffer tri-state noise reduction circuit
CMOS inverter having temperature and supply voltage variation compensation
Output buffer having capacitive drive shunt for reduced noise
Controlled slew rate buffer
Programmable output drive circuit
Power supply start up circuit for dynamic random access memory
Voltage regulator for programming non-volatile and electrically programmable memory cells
Semiconductor integrated circuit device with data output circuit
Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage Patent #: 5689460
ApplicationNo. 298968 filed on 04/26/1999
US Classes:327/112, Push-pull327/540, With voltage source regulating327/541With field-effect transistor
ExaminersPrimary: Lam, Tuan T.
Attorney, Agent or Firm
International ClassG05F 001/10
Foreign Application Priority Data1994-11-15 JP
AbstractA data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.