U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Data output circuit with reduced output noise

Patent 6163180 Issued on December 19, 2000. Estimated Expiration Date: Icon_subject April 26, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Output buffer tri-state noise reduction circuit
Patent #: 4877978
Issued on: 10/31/1989
Inventor: Platt

CMOS inverter having temperature and supply voltage variation compensation
Patent #: 4894561
Issued on: 01/16/1990
Inventor: Nogami

Output buffer having capacitive drive shunt for reduced noise
Patent #: 5017807
Issued on: 05/21/1991
Inventor: Kriz, et al.

Controlled slew rate buffer
Patent #: 5138194
Issued on: 08/11/1992
Inventor: Yoeli

Programmable output drive circuit
Patent #: 5153450
Issued on: 10/06/1992
Inventor: Ruetz

Power supply start up circuit for dynamic random access memory
Patent #: 5319601
Issued on: 06/07/1994
Inventor: Kawata, et al.

Voltage regulator for programming non-volatile and electrically programmable memory cells
Patent #: 5519656
Issued on: 05/21/1996
Inventor: Maccarrone, et al.

Semiconductor integrated circuit device with data output circuit
Patent #: 5570038
Issued on: 10/29/1996
Inventor: Makino, et al.

Semiconductor memory device with a voltage down converter stably generating an internal down-converted voltage Patent #: 5689460
Issued on: 11/18/1997
Inventor: Ooishi

Inventors

Application

No. 298968 filed on 04/26/1999

US Classes:

327/112, Push-pull327/540, With voltage source regulating327/541With field-effect transistor

Examiners

Primary: Lam, Tuan T.

Attorney, Agent or Firm

International Class

G05F 001/10

Foreign Application Priority Data

1994-11-15 JP

Abstract

A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

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