Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
January 11, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSolid state electromagnetic radiation detector with planarization layer Multilevel interconnect structure with air gaps formed between metal leads Method of fabricating porous dielectric material with a passivation layer for electronics applications Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers Method of making reliable metal leads in high speed LSI semiconductors using thermoconductive layers Method of forming a multilevel dielectric Multilevel interconnect structure with air gaps formed between metal leads Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits Method of making two-component nanospheres and their use as a low dielectric constant material for semiconductor devices Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits InventorsApplicationNo. 229382 filed on 01/11/1999US Classes:438/622, Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)216/2, ETCHING OF SEMICONDUCTOR MATERIAL TO PRODUCE AN ARTICLE HAVING A NONELECTRICAL FUNCTION257/E21.576, Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO)257/E21.581, Dielectric comprising air gaps (EPO)257/E23.144, Capacitive arrangements or effects of, or between wiring layers (EPO)257/E23.167, Insulating materials (EPO)438/619, Air bridge structure438/623, Including organic insulating material between metal levels438/702Plural coating stepsExaminersPrimary: Mills, GregoryAssistant: Hassanzadeh, P. Attorney, Agent or FirmInternational ClassesH01L 021/00H01L 021/70 H01L 021/77 AbstractA method for fabricating a hybrid low dielectric constant intermetal dielectric layer with improved reliability for multilevel electrical interconnections on integrated circuits is achieved. After forming metal lines for interconnecting the semiconductor devices, a protective insulating layer composed of a low-k fluorine-doped oxide (k=3.5) is deposited. A porous low-k spin-on dielectric layer (k less than 3) is formed in the gaps between the metal lines to further minimize the intralevel capacitance. A more dense low-k dielectric layer, such as FSG, is deposited on the porous layer to provide improved structural mechanical strength and over the metal lines to provide reduced intralevel capacitance. Via holes are etched in the FSG and are filled with metal plugs and the method can be repeated for additional metal levels to complete the multilevel interconnections on the integrated circuit.Field of SearchMultiple metal levels, separated by insulating layer (i.e., multiple level metallization)Including organic insulating material between metal levels Planarization Contacting multiple semiconductive regions (i.e., interconnects) Having planarization step Simultaneously by chemical and mechanical means Plug formation (i.e., in viahole) Utilizing chemical vapor deposition (i.e., CVD) Air bridge structure Plural coating steps ETCHING OF SEMICONDUCTOR MATERIAL TO PRODUCE AN ARTICLE HAVING A NONELECTRICAL FUNCTION ETCHING AND COATING OCCUR IN THE SAME PROCESSING CHAMBER Using coil to generate the plasma | |
