Nonvolatile semiconductor memory device and method of manufacturing the same
Patent 6157061 Issued on December 5, 2000. Estimated Expiration Date: 
August 27, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 27, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesNon-volatile semiconductor memory device Electrically erasable read only memory cell array having elongated control gate in a trench Electrically erasable and programmable semiconductor memory device with trench memory transistor and manufacturing method of the same Non-volatile memory device having a floating gate Patent #: 5350937 InventorAssigneeApplicationNo. 141324 filed on 08/27/1998US Classes:257/316, With additional contacted control electrode257/314, Variable threshold (e.g., floating gate memory device)257/315, With floating gate electrode257/E21.422, With floating gate (EPO)257/E29.308Programmable with more than two possible different levels (EPO)ExaminersPrimary: Tran, Minh LoanAssistant: Nguyen, Hoang Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/76H01L 029/788 Foreign Application Priority Data1997-08-29 JPAbstractA nonvolatile semiconductor memory device includes a vertical memory cell. The memory cell is constituted by at least a channel portion, a drain and a source, first and second floating gates, and a control gate. The channel portion is vertically formed on a semiconductor substrate. The drain and the source are formed at upper and lower positions of the channel portion to form a channel in the channel portion. The first floating gate is formed on part of a side portion of the channel portion via a gate insulating film. The second floating gate is formed on the side portion of the channel portion in a region without the first floating gate. The control gate is formed outside the first and second floating gates via an insulating isolation film. A method of manufacturing the nonvolatile semiconductor memory device is also disclosed.Field of SearchWith thin insulator region for charging or discharging floating electrode by quantum mechanical tunnelingMultiple insulator layers (e.g., MNOS structure) With means to facilitate light erasure Plural additional contacted control electrodes With irregularities on electrode to facilitate charging or discharging of floating electrode With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) Variable threshold (e.g., floating gate memory device) With floating gate electrode With additional contacted control electrode Separate control electrodes for charging and for discharging floating electrode Additional control electrode is doped region in semiconductor substrate Plural gate electrodes or grid shaped gate electrode Having additional gate electrode surrounded by dielectric (i.e., floating gate) Including additional field effect transistor (e.g., sense or access transistor, etc.) Including forming gate electrode in trench or recess in substrate Textured surface of gate insulator or gate electrode Multiple interelectrode dielectrics or nonsilicon compound gate insulator Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) Tunneling insulator Tunneling insulator | |
