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Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks

Patent 6154819 Issued on November 28, 2000. Estimated Expiration Date: Icon_subject May 11, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Inventors

Application

No. 076298 filed on 05/11/1998

US Classes:

711/163, Access limiting365/185.33, Flash711/103, Programmable read only memory (PROM, EEPROM, etc.)711/152, Memory access blocking711/173Memory partitioning

Examiners

Primary: Nguyen, Hiep T.

Attorney, Agent or Firm

International Class

G06F 012/14

Abstract

An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

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