Sense amplifier for a ROM having a multilevel memory cell
Non-volatile semiconductor memory device with facility of storing tri-level data
Apparatus and method for reading multi-level data stored in a semiconductor memory
Multi-stage sense amplifier for read-only memory having current comparators
Non-volatile memory device and apparatus for reading a non-volatile memory array
Multi-stage ROM wherein a cell current of a selected memory cell is compared with a plurality of constant currents when driven to read voltages
High read speed multivalued read only memory device
Parallel-dichotomic serial sensing method for sensing multiple-level non-volatile memory cells, and sensing circuit for actuating such method Patent #: 5729490
ApplicationNo. 465351 filed on 12/16/1999
US Classes:365/185.21, Sensing circuitry (e.g., current mirror)365/104, Transistors365/168, Ternary365/185.03, Multiple values (e.g., analog)365/185.2Reference signal (e.g., dummy cell)
ExaminersPrimary: Tran, Andrew Q.
Attorney, Agent or Firm
Foreign Patent References
International ClassesG11C 016/26
AbstractA reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle, sensing circuit coupled to the multibit memory cell which compares current from the multibit memory cell to a first reference current and a second reference current, and produces a first output during the first time interval having a first logic state, if the current from the cell exceeds the first reference current and a second logic state if the current from the cell is less than the first reference current, and produces a second output during the second time interval having a first logic state if the current from the cell is less than the second reference current and greater than the first reference current, and a second logic state if the current from the cell is greater than the first reference current and greater than the second reference current.