Method of forming a logic array for a decoder
May 17, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFormation and planarization of silicon-on-insulator structures Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers Integrated circuit Vertical type MOS transistor and method of formation thereof Method of making ultra dense dram cells Semiconductor integrated circuit device Sidewall capacitor DRAM cell CMOS logic array layout Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor InventorsAssigneeApplicationNo. 313049 filed on 05/17/1999US Classes:438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)257/E27.103, Electrically programmable ROM (EPO)438/157, Plural gate electrodes (e.g., dual gate, etc.)438/268, Vertical channel438/269Utilizing epitaxial semiconductor layer grown through an opening in an insulating layerExaminersPrimary: Smith, MatthewAssistant: Malsawma, Lex H. Attorney, Agent or FirmInternational ClassesH01L 021/336H01L 021/84 AbstractA programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F2 is needed per bit of logic, where F is the minimum lithographic feature size.Other References
Field of SearchHaving additional gate electrode surrounded by dielectric (i.e., floating gate)Vertical channel Utilizing epitaxial semiconductor layer grown through an opening in an insulating layer Plural gate electrodes (e.g., dual gate, etc.) Multiple parallel current paths (e.g., grid gate, etc.) Particular decoder or driver circuit FLOATING GATE Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) With plural, separately connected, gate electrodes in same device Gate controls vertical charge flow portion of channel (e.g., VMOS device) Gate electrode in groove Plural gate electrodes or grid shaped gate electrode | |
