Method for forming self-aligned features
October 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing a semiconductor device having conductive and insulating portions formed of a common material utilizing selective oxidation and angled ion-implantation Interrupted polysilanes useful as photoresists Methods of forming channels and vias in insulating layers Boron out-diffused surface strap process Method of manufacturing a semiconductor device using an implantation mask Fabrication method for high-capacitance storage node structures Patent #: 5776660 InventorsApplicationNo. 183338 filed on 10/30/1998US Classes:438/618, Contacting multiple semiconductive regions (i.e., interconnects)257/E21.027, Photolith ographic process (EPO)257/E21.577, By forming via holes (EPO)257/E21.579, For "dual damascene" type structures (EPO)430/312, Including multiple resist image formation438/637, With formation of opening (i.e., viahole) in insulative layer438/736Utilizing multilayered maskExaminersPrimary: Fourson, GeorgeAttorney, Agent or FirmInternational ClassH01L 021/476.3AbstractThe present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.Other References
Field of SearchIncluding multiple resist image formationEtching of substrate and material deposition Including etching substrate Contacting multiple semiconductive regions (i.e., interconnects) Utilizing multilayered mask With formation of opening (i.e., viahole) in insulative layer Utilizing multilayered mask |
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