Insulated gate type field effect transistor and method of manufacturing the same
April 3, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for planarizing semiconductor substrates Integrated circuit planarization by mechanical polishing Method of forming a via having sloped sidewalls Method for planarizing semiconductor wafers with a non-circular polishing pad Integrated radiation pixel detector with PIN diode array Method of manufacturing a semiconductor device Semiconductor substrate for gettering Four layer overvoltage protection device having buried regions aligned with shorting dots to increase the accuracy of overshoot voltage value Patent #: 5479031 InventorsAssigneeApplicationNo. 054493 filed on 04/03/1998US Classes:438/268, Vertical channel257/E21.318, Of silicon body, e.g., for gettering (EPO)257/E21.383, Vertical insulated gate bipolar transistor (EPO)257/E29.037, Anode regions of thyristors or gated bipolar-mode devices (EPO)257/E29.198, Transistor with vertical current flow (EPO)438/272, Totally embedded in semiconductive layers438/273Having integral short of source and base regionsExaminersPrimary: Elms, RichardAssistant: Lebentritt, Michael S. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/336Foreign Application Priority Data1995-03-07 JPAbstractIn an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.Other References
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