Low-power column parallel ADC in CMOS image sensors
Patent 6137432 Issued on October 24, 2000. Estimated Expiration Date: 
November 4, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 4, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDual-slope analog-to-digital converter with voltage to current converter Ripsaw analog-to-digital converter and method CMOS image sensor with pixel level A/D conversion Imaging system with 1-N Parallel channels, each channel has a programmable amplifier and ADC with serial controller linking and controlling the amplifiers and ADCs Patent #: 5613156 InventorAssigneeApplicationNo. 187308 filed on 11/04/1998US Classes:341/169, Input signal compared with linear ramp341/155, Analog to digital conversion341/170Input signal compared with nonlinear rampExaminersPrimary: Young, BrianAssistant: Kost, Jason L. W. Attorney, Agent or FirmInternational ClassH03M 001/56AbstractA low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.Other References
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