Method of fabricating double poly-gate high density multi-state flat mask ROM cells
June 19, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMask ROM process with self-aligned ROM code implant Method for fabricating read-only-memory devices with self-aligned code implants Method of manufacturing a mask read only memory (ROM) for storing multi-value data Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby Mask ROM process with self-aligned ROM code implant Manufacturing method for ROM array with minimal band-to-band tunneling Method of fabricating tetra-state mask read only memory Patent #: 5891779 InventorApplicationNo. 099699 filed on 06/19/1998US Classes:438/276, Introducing a dopant into the channel region of selected transistors257/E21.671, Doping programmed, e.g., mask ROM (EPO)257/E27.102, Read-only memory, ROM, structure (EPO)438/278After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.)ExaminersPrimary: Fourson, GeorgeAssistant: Abbott, Elizabeth Attorney, Agent or FirmInternational ClassH01L 021/336AbstractA method to fabricate double poly gate high-density multi-state flat mask ROM cells on a silcon substrate is disclosed. The method comprises the following steps. Firstly, an in-situ n+ first polysilicon/pad oxide layer is deposited on the silicon substrate, and then an ARC layer such as nitride layer is deposited to improve the resolution during the lithography process for pateterning a first formed word line. After forming a plurality of dual nitride spacers on sidewalls of the first patterned gate, a first photoresist coating on all resultant surfaces except the two predetermined regins, a first boron or BF2+ coding implant into the silicon substrate is carried out. The photoresist is then stripped and an oxidaiton process conducted in O2 ambient to grow oxide layers on all surfaces of the silicon substrate using the nitride layer as a hard mask. Subsequently, a second silicon layer (polysilicon or amorphous silicon) is deposited to refill all of the spaces between the two nearest first formed gates, and then a thick oxide layer is formed on the second polysilicon layer. After that, a CMP process is done to form a flat surface using the nitride as an etching stopper. Finally, a second photoresist mask is formed on all surfaces except a second predetermined region. Then a high energy, second boron coding implant is implanted into said predetermined regions to form the multi-state mask ROM.Other References
Field of SearchIntroducing a dopant into the channel region of selected transistorsAfter formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.) Including multiple implantation steps Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.) After formation of source or drain regions and gate electrode With plural, separately connected, gate electrodes in same device Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode) | |
