Semiconductor device and fabrication process thereof
Patent 6130154 Issued on October 10, 2000. Estimated Expiration Date: 
March 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing a semiconductor device using a silicon fluoride oxide film Polishing methods for forming a contact plug Methods of forming electrical interconnects on integrated circuit substrates using selective slurries Patent #: 5960317 InventorsAssigneeApplicationNo. 049931 filed on 03/30/1998US Classes:438/627, At least one layer forms a diffusion barrier257/E21.276, Deposition of halogen doped silicon oxide, e.g., fluorine doped silicon oxide (EPO)257/E21.576, Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO)438/624, Separating insulating layer is laminate or composite of plural insulating materials438/625, At least one metallization level formed of diverse conductive layers438/636, Including use of antireflective layer438/648, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/783Insulative material having impurity (e.g., for altering physical characteristics, etc.)ExaminersPrimary: Niebling, John F.Assistant: Ghyka, Alexander Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/476.3H01L 021/31 Foreign Application Priority Data1997-03-31 JPAbstractA semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.Other References
Field of SearchSeparating insulating layer is laminate or composite of plural insulating materialsAt least one metallization level formed of diverse conductive layers At least one layer forms a diffusion barrier Including use of antireflective layer Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) Insulative material having impurity (e.g., for altering physical characteristics, etc.) | |
