Patent 6125062 Issued on September 26, 2000. Estimated Expiration Date: August 26, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
365/189.07, Including signal comparison257/314, Variable threshold (e.g., floating gate memory device)257/E21.209, Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)257/E27.084, Dynamic random access memory, DRAM, structure (EPO)257/E29.301Programmable by two single electrons (EPO)
A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.
Other References
Lingjie Guo et al., "A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel," Appl. Phys. Lett. 70(7):850-852, Feb. 1997
Lingjie Guo et al., "Fabrication and characterization of room temperature silicon single electron memory," J. Vac. Sci. Technol. B 15(6):2840-2843, Nov./Dec. 1997
Rodrigo Martins et al., "Transport properties of doped silicon oxycarbide microcrystalline films produced by spatial separation techniques," Solar Energy Materials and Solar Cells 41/42:493-517, 1996
Anri Nakajima et al., "Room Temperature Operation of Si Single-Electron Memory with Self-Aligned Floating Dot Gate," IEDM 96, pp. 952-954, 1996
Anri Nakajima et al., "Room Temperature Operation of Si Single-Electron Memory with Self-Aligned Floating Dot Gate," Appl. Phys. Lett. (70)13:1742-1744, Mar. 1997
Anri Nakajima et al., "Si Single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process," Appl. Phys. Lett. 71(3):353-355, Jul. 1997
Sandip Tiwari et al., "Single charge and confinement effects in nano-crystal memories," Appl. Phys. Lett. 69(9):1232-1234, Aug. 1996
Hussein I. Hanafi, "Fast and Long Retention-Time Nano-Crystal Memory," IEEE Transactions on Electron Devices 43(9):1553-1558, Sep. 1996
G. Craciun et al., "On the morphology of porous silicon layers obtained by electrochemical method," 1995 International Semiconductor Conference, 18th Edition, pp. 331-334, Oct. 1995
Tomoyuki Ishii et al., "A 3-D Single-Electron-Memory Cell Structure with 2F2 per bit," IEDM, pp. 924-926, 1997
K. Yano et al., Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage, ISSCC Digest of Technical Papers, pp. 266-267, Feb. 1996
K. Yano et al., "A 128Mb Early Prototype for Gigascale Single-Electron Memories," ISSCC Digest of Technical Papers, pp. 344-345., Feb. 1998
Haroon Ahmed and Kazuo Nakazato, "Single-electron devices," Microelectronic Engineering 32:297-315, 1996
Haroon Ahmed, "Single electron electronics: Challenge for nanofabrication," J. Vac. Sci. Technol. B. 15(6):2101-2108, Nov./Dec. 1997
Tomoyuki Ishii, "Verify: Key to the Stable Single-Electron-Memory Operation," IEDM, pp. 171-174, 1997
Valery M. Dubin, "Formation mechanism of porous silicon layers obtained by anodization of monocrystalline n-type silicon in HF solutions," Surface Science 274:82-92, 1992
Jian-Shing Luo and Wen-Tai Lin, "Localized epitaxial growth of hexagonal and cubic SiC films on Si by vacuum annealing," Appl. Phys. Lett. 69(7):916-918, Aug. 1996
Donato Montanari et al., "Novel Level-Identifying Circuit for Flash Multilevel Memories," IEEE Journal of Solid-State Circuits 35(7):1090-1095, Jul. 1998
Nae-In Lee et al., "Highly Reliable Polysilicon Oxide Grown by Electron Cyclotron Resonance Nitrous Oxide Plasma," IEEE Electron Device Letters 18(10):486-488, Oct. 1997
Masato Tarakomori and Hideaki Ikoma, "Low-Temperature Si Oxidation Using Inductively Coupled Oxygen-Argon Mixed Plasma," Jpn. J. Appl. Phys. 36:5409-5415, 1997
Jin-Woo Lee et al., "Oxidation of Silicon Using Electron Cyclotron Resonance Nitrous Oxide Plasma and Its Application to Polycrystalline Silicon Thin Film Transistors," Journal of the Electrochemical. Society 144(9):3283-3287, Sep. 1997
W.S. Park et al, "Growth of polycrystalline silicon at low temperature on hydrogenated microcrystalline silicon seed layer," Mat. Res. Soc. Symp. Proc. 467:403-408, 1997
T. Nishimiya et al., "Novel Plasma Control Method in PECVD for Preparing Microcrystalline Silicon," Mat. Res. Soc. Symp. Proc. 467:397-401, 1997
Constantin Papadas et al., "Modeling of the Intrinsic Retention Characteristics of FLOTOX EEPROM Cells Under Elevated Temperature Conditions," IEEE Transactions on Electron Devices 42(4):678-682, Apr. 1995
Brian Dipert and Lou Hebert, "Flash memory goes mainstream," IEEE Spectrum, pp. 48-52, Oct. 1993
Joao Pedro Conde et al., "Amorphous and Microcrystalline Silicon Deposited by Low-Power Electron-Cyclotron Resonance Plasma-Enhanced Chemical-Vapor Deposition," Japanese Journal of Applied Physics 36:38-49, Jan. 1997
D.M. Wolfe et al., "Low-Temperature (450° C) Poly-Si Thin Film Deposition on SiO2 and Glass Using a Microcrystalline-Si Seed Layer," Mat. Res. Soc. Symp. Proc. 472:427-432, 1997
Yasuo Tarui, "Flash Memory Features Simple Structure, Superior integration," JEE 30:84-87, Sep. 199
August 26, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
