Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
July 14, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh-performance, superscalar-based computer system with out-of-order instruction execution System for handling load and/or store operations in a superscalar microprocessor Computer organization for multiple and out-of-order execution of condition code testing and setting instructions High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations Lookahead register value generator and a superscalar microprocessor employing same Apparatus for providing memory and register operands concurrently to functional units Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received System and method for assigning tags to control instruction processing in a superscalar processor Dispatching instructions in a processor supporting out-of-order execution InventorAssigneeApplicationNo. 115123 filed on 07/14/1998US Classes:712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/217, Scoreboarding, reservation station, or aliasing712/218Commitment control or register bypassExaminersPrimary: An, Meng-Ai T.Assistant: Benson, Walter Attorney, Agent or FirmForeign Patent References
International ClassC06F 009/38AbstractA processor includes a lookahead address/result calculation unit which is configured to receive operand information (either the operand or a tag identifying the instruction which will produce the operand value) corresponding to the source operands of one or more instructions. If the operands are available, lookahead address/result calculation unit may generate either a lookahead address for a memory operand of the instruction or a lookahead result corresponding to a functional instruction operation of the instruction. The lookahead address may be provided to a load/store unit for early initiation of a memory operation corresponding to the instruction. The lookahead result may be provided to a speculative operand source (e.g. a future file) for updating therein. A lookahead state for a register may thereby be provided early in the pipeline. Subsequent instructions may receive the lookahead state and use the lookahead state to generate additional lookahead state early. On the other hand, the subsequent instructions may receive the lookahead state and hence may be prepared for execution upon dispatch to an instruction window (as opposed to waiting in the instruction window for execution of the prior instruction). In one embodiment, the processor also includes an operand collapse unit configured to collapse the lookahead results into subsequent, concurrently decoded instructions (intraline dependencies). Additionally, the operand collapse unit may be configured to collapse a compare instruction into a subsequent branch instruction which depends upon the result of the compare.Other References
Field of SearchDYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTIONSuperscalar INSTRUCTION ISSUING Simultaneous issuance of multiple instructions Scoreboarding, reservation station, or aliasing Commitment control or register bypass Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.) To macro-instruction routine Arithmetic operation instruction processing Logic operation instruction processing Instruction modification based on condition Cache pipelining Memory access pipelining | |
