Multichannel digital audio decoding method and apparatus
Patent 6108584 Issued on August 22, 2000. Estimated Expiration Date: 
July 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 9, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for generating a multi-channel audio decoder matrix Integrated MPEG audio decoder and signal processor Fast requantization apparatus and method for MPEG audio decoding Multi-standard decompression and/or compression device SRAM having enhanced cell ratio Patent #: 5955746 InventorAssigneeApplicationNo. 890049 filed on 07/09/1997US Classes:700/94, Digital audio data processing system381/22Variable decoderExaminersPrimary: Isen, Forester W.Assistant: Pendleton, Brian T. Attorney, Agent or FirmInternational ClassesG06F 017/00H04R 005/00 AbstractIn digital audio decoding, the compressed data of the first two channels of a frame of MPEG multichannel audio are received, parsed and stored in plural spaced sub-blocks of buffer memory. Then, coding information of the same frame is received and interpreted. If the signal includes MPEG-2 multichannel audio, then compressed data of the remaining channels of the frame are received, parsed and interleaved in the sub-blocks. The sub-blocks are read from the buffer and decoded, sub-block by sub-block, transformed into decoded output data of all of the channels for simultaneous output to output devices. Less than 8K-bits read to local memory can be decoded to produce full multiple channel output. A memory controller accesses non-contiguous areas of the buffer memory and reads and writes differing sizes of data blocks. Substantial savings in both on and off chip memory are provided.Other References
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