I/O protocol for highly configurable multi-node processing system
February 6, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInter-subsystem communication system Low-end high-performance switch subsystem architecture Multiprocessor computer system Generic high bandwidth adapter providing data communications between diverse communication networks and computer system Input output control system for transferring control programs collectively as one transfer unit designated by plurality of input output requests to be executed Data transmitting/receiving method using distributed path control in data switching system Method and apparatus for reducing propagation latency in a high speed crossbar switch Independent channel coupled to be shared by multiple physical processing nodes with each node characterized as having its own memory, CPU and operating system image Patent #: 5907684 InventorsAssigneeApplicationNo. 020199 filed on 02/06/1998US Classes:712/1, PROCESSING ARCHITECTURE345/472, Scaling709/215, Partitioned shared memory709/217, REMOTE DATA ACCESSING709/221, Reconfiguring709/224, Computer network monitoring709/239, Alternate path routing710/36, Input/Output access regulation710/316Path selecting switchExaminersPrimary: Asta, Frank J.Assistant: Prieto, Beatriz Attorney, Agent or FirmForeign Patent References
International ClassesG06F 015/163G06F 015/17 AbstractA method for transferring data from a first node to a second node in a multi-processor system is described. The multi-processor system comprises a plurality of nodes coupled to an interconnect fabric via an interconnect fabric interface, the nodes comprising a compute node and an I/O node, the I/O node coupled to a plurality of data storage devices. The method comprises the steps of generating a I/O request packet in a first node in response to an I/O request from an application executing in a first node, transmitting the data request packet to the second node via the interconnect fabric, and executing the destination interconnect channel program to extract the debit ID to transfer the data request to the second node buffer. In one embodiment, the I/O packet includes a data transfer request, an interconnect destination channel program, a first debit ID designating a second node buffer where the data request will be transmitted, and a first credit ID designating a first node buffer where the data responsive to the I/O request will be transmitted.Field of SearchReconfiguringComputer network monitoring Alternate path routing REMOTE DATA ACCESSING Partitioned shared memory Configuration initialization Input/Output access regulation Reliability and availability Fault recovery By masking or reconfiguration Fault locating (i.e., diagnosis or testing) Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) Additional processor for in-system fault locating (e.g., distributed diagnosis program) Bypass an inoperative switch or inoperative element of a switching system Of a switching system PATHFINDING OR ROUTING Mode switching Shared memory area | |
