Patent ReferencesMicroprocessor having precoder unit and main decoder unit operating in pipeline processing manner Apparatus and method for resolving dependencies among a plurality of instructions within a storage device Superscalar processor with a multi-port reorder buffer Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue Superscalar microprocessor including flag operand renaming and forwarding apparatus Data processor with an execution unit for performing load instructions and method of operation Floating point stack and exchange instruction Lookahead register value generator and a superscalar microprocessor employing same Floating point stack and exchange instruction Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register InventorAssigneeApplicationNo. 115115 filed on 07/14/1998US Classes:712/23, Superscalar712/215Simultaneous issuance of multiple instructionsExaminersPrimary: Coleman, EricAttorney, Agent or FirmForeign Patent References
International ClassG06F 009/38AbstractAn apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a register rename unit, which reassigns the rename register associated with the source register to the destination register. In one particular embodiment, the lookahead unit attempts to accelerate moves from a base pointer register to a stack pointer register (and vice versa). An embodiment of the lookahead unit generates lookahead values for the stack pointer register by maintaining cumulative effects of the increments and decrements of previously dispatched instructions. The cumulative effects of the increments and decrements prior to a particular instruction may be added to a previously generated value of the stack pointer register to generate a lookahead value for that particular instruction. For such an embodiment, reassigning the rename register as described above may thereby provide a valid value for the stack pointer register, and hence may allow for the generation of lookahead stack pointer values for instructions subsequent to the move instruction to proceed prior to execution of the move instruction. The present embodiment of the register rename unit may also assign the destination rename register selected for the move instruction to the source register of the move instruction (i.e. the rename tags for the source and destination are "swapped").Other References
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