Method of providing a gettering scheme in the manufacture of silicon-on-insulator (SOI) integrated circuits
December 23, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of dicing a semiconductor wafer Method of dicing semiconductor wafers which produces shards less than 10 microns in size Method to getter contamination in semiconductor devices Method of manufacturing SOI semiconductor device Method of making linear capacitors for high temperature applications Method of making a structure for top surface gettering of metallic impurities Method for detaching chips from a wafer Method of fabricating semiconductor chips separated by scribe lines used for endpoint detection Method and structure for front-side gettering of silicon-on-insulator substrates Semiconductor device and method for fabricating the same InventorsAssigneeApplicationNo. 996672 filed on 12/23/1997US Classes:438/462, Having specified scribe region structure (e.g., alignment mark, plural grooves, etc.)257/E21.32, Of silicon on insulator (SOI) (EPO)257/E21.561, Using semiconductor or insulator technology, i.e., SOI technology (EPO)438/402, And gettering of substrate438/465, Having a perfecting coating438/476By layers which are coated, contacted, or diffusedExaminersPrimary: Mulpuri, SavitriAttorney, Agent or FirmInternational ClassH01L 021/301AbstractA method of providing a gettering scheme in the manufacture of individual Silicon-On-Insulator (SOI) integrated circuits from an SOI wafer containing a number of such integrated circuits includes the steps of providing a gettering material in scribe lanes along which the SOI wafer is to be diced to obtain the individual SOI integrated circuits. The SOI wafer is then diced along the scribe lanes, leaving a portion of the gettering material on the diced edges of the individual integrated circuits. This method provides a simple and effective method for gettering in SOI technology in which diffusing impurities can be trapped before diffusing into the active area of the integrated circuits.Field of SearchAnd gettering of substrateFORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE Having substrate registration feature (e.g., alignment mark) Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.) GETTERING OF SUBSTRATE By layers which are coated, contacted, or diffused By vapor phase surface reaction SEMICONDUCTOR SUBSTRATE DICING Having specified scribe region structure (e.g., alignment mark, plural grooves, etc.) Having a perfecting coating | |
