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US Patent 6092174 - Dynamically reconfigurable distributed integrated circuit processor and method
US Patent Issued on July 18, 2000
Estimated Patent Expiration Date:
June 1, 2018Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
June 1, 2018Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA dynamically reconfigurable distributed integrated circuit processor has at least one two-layer matrix in which a first layer has operative microcomputer modules (1) with local memory (2) grouped in computational clusters (5) and a second layer has a network of global communications connecting buses (7, 8) with packet decoders in coherence with the first layer. All components of the basic operating units are micro programmable and in universal communication selectively throughout separate operative microcomputer modules and throughout the computational clusters. Electrical conductivity of components is variable for select speed, timing and factors. A use method is described. | InventorAssigneeApplicationNo. 088165 filed on 06/01/1998US Classes:712/15, Reconfiguring712/11, Array processor element interconnection712/16, Array processor operation712/23SuperscalarField of Search712/37, Programmable (e.g., EPROM)712/23, Superscalar712/11, Array processor element interconnection712/15, Reconfiguring712/16Array processor operationExaminersPrimary: An, Meng-Ai T.Assistant: Monestime, Mackly Attorney, Agent or FirmUS Patent References4851995, Programmable variable-cycle clock circuit for skew-tolerant array processor architectureIssued on: 07/25/1989 Inventor: Hsu , et al.5020059, Reconfigurable signal processor Issued on: 05/28/1991 Inventor: Gorin, et al.5361367, Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors Issued on: 11/01/1994 Inventor: Fijany, et al.5457410, Architecture and interconnect scheme for programmable logic circuits Issued on: 10/10/1995 Inventor: Ting5535406, Virtual processor module including a reconfigurable programmable matrix Issued on: 07/09/1996 Inventor: Kolchinsky5535408, Processor chip for parallel processing system Issued on: 07/09/1996 Inventor: Hillis5590284, Parallel processing data network of master and slave transputers controlled by a serial control network Issued on: 12/31/1996 Inventor: Crosetto5600845, Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor Issued on: 02/04/1997 Inventor: Gilson5649106, Parallel computer with reconstruction of processor clusters Issued on: 07/15/1997 Inventor: Tsujimichi, et al.5649179, Dynamic instruction allocation for a SIMD processor Issued on: 07/15/1997 Inventor: Steenstra, et al.5689661, Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems Issued on: 11/18/1997 Inventor: Hayashi, et al.5892962FPGA-based processor Issued on: 04/06/1999 Inventor: Cloutier International ClassG06F 015/00 |
