Dynamically reconfigurable distributed integrated circuit processor and method
June 1, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable variable-cycle clock circuit for skew-tolerant array processor architecture Reconfigurable signal processor Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors Architecture and interconnect scheme for programmable logic circuits Virtual processor module including a reconfigurable programmable matrix Processor chip for parallel processing system Parallel processing data network of master and slave transputers controlled by a serial control network Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor Parallel computer with reconstruction of processor clusters Dynamic instruction allocation for a SIMD processor InventorAssigneeApplicationNo. 088165 filed on 06/01/1998US Classes:712/15, Reconfiguring712/11, Array processor element interconnection712/16, Array processor operation712/23SuperscalarExaminersPrimary: An, Meng-Ai T.Assistant: Monestime, Mackly Attorney, Agent or FirmInternational ClassG06F 015/00AbstractA dynamically reconfigurable distributed integrated circuit processor has at least one two-layer matrix in which a first layer has operative microcomputer modules (1) with local memory (2) grouped in computational clusters (5) and a second layer has a network of global communications connecting buses (7, 8) with packet decoders in coherence with the first layer. All components of the basic operating units are micro programmable and in universal communication selectively throughout separate operative microcomputer modules and throughout the computational clusters. Electrical conductivity of components is variable for select speed, timing and factors. A use method is described. | |
