Method of single step damascene process for deposition and global planarization

Patent 6090239 Issued on July 18, 2000. Estimated Expiration Date:

August 2, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
Patent #: 5723387
Issued on: 03/03/1998
Inventor: Chen

Method of electrochemical mechanical planarization
Patent #: 5807165
Issued on: 09/15/1998
Inventor: Uzoh, et al.

Apparatus for electrochemical mechanical planarization Patent #: 5911619
Issued on: 06/15/1999
Inventor: Uzoh, et al.

Inventors

Assignee

LSI Logic Corporation

Application

No. 365440 filed on 08/02/1999

US Classes:

156/345.12, With mechanical polishing (i.e., CMP-chemical mechanical polishing)257/E21.304, By chemical mechanical polishing (CMP) (EPO)451/67, With nonabrading means451/73, Adjunct451/287, Planar surface abrading451/290Disk or wheel abrader

Examiners

Primary: Utech, Benjamin L.
Assistant: Champagne, Donald L.

Attorney, Agent or Firm

Beyer & Weaver, LLP

International Class

C23F 001/02

Abstract

A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad 104 providing a surface against which a surface of an integrated circuit substrate 116 is polished; (ii) an anode 103 on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source 106 electrically connecting the anode to the integrated circuit substrate in such a way that when a voltage is applied from the voltage source in the presence of slurry 114 admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate. A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously is also described.

Other References

Morand et al., "Copper Integration in Self Aligned Dual Damascene Architecture", 1997, Symposium on VLSI Technology Digest of Technical Papers, pp. 31-32
Tsuchiya et al., "Ultra-Low Resistance Direct Contact Cu Via Technology Using In-Situ Chemical Vapor Cleaning", 1997, Symposium on VLSI Technology Digest of Technical Papers, pp. 59-6